CAD for complex printed circuit boards

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Allegro comes as a base license and a set of additional options that are an “add-on” to the base license and provide more powerful, specialized functionality for various applications.

Benefits of Cadence Allegro and OrCAD

Stability and error-free operation of the program

Scalable from low-cost OrCAD to powerful Allegro options

Huge selection of reference designs and libraries in Allegro format

Top-notch modeling, integration with PSpice and Sigrity

Convenient table editor of Constraint Manager rules

High efficiency when working with complex boards

Why do developers choose Cadence Allegro?

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A schematic editor compatible with OrCAD and the ability to import high-quality schematics, boards and libraries from P-CAD, coupled with a simple and user-friendly interface, make Cadence Allegro the best option for a gradual “seamless” transition to new technologies. The reports built into Allegro make it possible to display design documentation according to the ESKD directly from CAD.

A convenient connection between the schematic editor and the PCB editor allows you to “drag” a component from the schematic onto the board when placing it, select a component on the schematic and see it on the board, highlight a pin or net on the board and see it on the schematic. The functionality of a unified library of enterprise components reduces the number of errors associated with the human factor.

You can use the widest range of library components not only from the standard supply, but also from Internet portals such as DigiKey, ActiveParts. The resulting components can be installed on the circuit directly from the Internet, and then they can be adjusted and saved into a single library of enterprise electronic components.

Powerful manual routing functionality allows you to instantly route single signals, differential pairs, buses, and simply grouped sets of connections. The signal length equalization system effectively meets all modern requirements for tracing high-speed interfaces such as PCIe, Ethernet, HDMI, DDR (T-connections, Fly-By), etc.

Full integration with enterprise component libraries, PDM systems (SolidWorks EPDM, Windchill, TeamCenter, etc.), with mechanical CAD systems (Compass 3D, SolidWorks, Creo, etc.), the ability to import and export STEP models of components, housing and printed circuit assembly make Cadence Allegro an ideal solution for large enterprises developing complex electronics.

Comparison with other, simpler CAD systems

Here's what the developers say after switching to Allegro:

This system is much more stable - and those CAD systems in which we worked before constantly froze or crashed on complex projects

The tabular rules editor is much more convenient and easier to use than rules in the form of “expressions”, and is also much more powerful.

Online checks do not slow down the CAD work at all - but previously we had to turn them off or minimize their number, and it took so long to complete the final DRC check.

The built-in calculation of impedance and layer structure is very useful - this sets Allegro apart from other CAD systems.

In Allegro there is no such problem as "incomplete connection of lines to pads". This means that my chain length rules will always be followed correctly.

Unlike other CAD systems, where old errors are not corrected and new ones are created, in Allegro we see the emergence of new functionality and careful work to correct noticed errors every quarter.

It’s very convenient to have the options window for the current command, object selection filter, and layer visibility control constantly open - unlike other CAD systems, where you have to constantly rummage through menus and windows.

Allegro has wonderful options for customizing hotkeys and mouse control functions.

When working with very large projects, unlike other CAD systems, the system does not crash or slow down.

The function of multiplying fragments (repeating nodes) works amazingly - it never fails, and does not require the creation of hierarchical schemes.

Allegro has a powerful pre-topological signal integrity analysis system built into it, with high reliability of the results, and it can and should really be used for work.

The analog-to-digital modeling system PSPICE is the best solution, especially with the Advanced Analysis function and the construction of behavioral models in C++.

Very good Russian-language support and training.

Possibility of high-quality import of old projects from P-CAD, Altium, PADS.

The system for working with polygons is amazing in terms of convenience and quality - it allows you to lay from 50 to 100 polygons per day without much effort - and does not slow down. Moreover, setting properties for polygons, pins, holes - everything is done on the fly and very quickly. Polygons are instantly dynamically updated during all topology editing operations.

Linux support is also an important feature.

The scalability of the solution and floating licenses allow you to get the optimal price for a workstation - from 150 thousand rubles, which no competing system can compare with.

Advanced options, such as High Speed, Team Design, offer functionality that other, simpler CAD systems generally do not have, for example, control of delays inside the chips, delay in the via, automatic alignment of the length of DDR signals, auto-phase alignment in diff .paired with dynamic tracking of mismatches.

Description of Cadence Allegro

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Allegro Design Entry Capture CIS circuit editor - advantages

Compatible with the popular OrCAD Capture editor

Ability to import schematics from PCAD and Altium

Possibility of outputting documentation using ESKD

Huge library of standard symbols (over 44,000)

Online library of components (over 15 million)

Online store for applications, IBIS models, SPICE models and libraries

Ability to view component footprint

Print diagrams to smart PDF with easy navigation

Setting and simultaneous automatic routing of signal groups

Simultaneous auto-bus connection

Setting “rooms” for further tracing

Automated laying of connections on the diagram

Powerful Tcl/Tk scripting language for writing routines

Online verification of DRC schemes, including custom rules

Backward and forward annotation (swapping pins or elements)

Cross-link with PCB editor (select and highlight)

Import and export FPGA pin tables when creating a symbol

Managing “versions” in a diagram

Convenient mechanism for visual checking of multi-page diagrams

Library management system Component Information System (Capture CIS)

Component database built into the schematic editor

Functionality of a unified database of enterprise components

Integration with PDM systems: SolidWorks EPDM, Windchill,
T-Flex, Search, etc.

Interface to ERI relational databases (SQL, MS Access, Excel)

Possibility of parametric search for required components

Managing the “applicability” of ERI, controlling access to the database

Ability to connect 3D models and datasheets to ERI

Search for ERI in the DigiKey, Mouser, etc. catalogs from the circuit editor

Editor of conventional graphic symbols (UGO)

Ability to extract and correct a symbol from a diagram

Ability to create UGO from an Excel table or datasheet

Component Footprint Editor

Convenient and powerful “wizard” for creating components

Possibility of creating free-form platforms

Utility for auto-creating components according to IPC-7351

PCB editor (Allegro PCB Designer), basic license capabilities

Import from PCAD, Altium and other CAD systems

Importing a PCB structure from DXF, IDF or STEP

Layer stack editor, impedance calculator

Semi-transparent display of layers

Net name display on conductor, land and pin

Ability to work with the board in “mirror” display

Placing groups of components by selecting directly from the diagram

Auto-alignment of component groups

Full support for differential pair tracing

Automatic creation of “Fan-out”

Automatic “fine-tuning” of connections

Use formulas to set length alignment rules

Electrical Rules and Limitations
(ECSet - reflections, delays, crosstalk)

Accounting for Via Delays

Taking into account the delay spread inside microcircuits

Auto-placement of groups of holes along routes

Control of the passage of conductors over slots in polygons

Possibility of using reverse drilling

Auto-crop, push, jump when tracing

Convenient subsystem for drawing a routing plan

Automatic creation and auto-alignment of markings

Fast export of gerber files, DXF and ODB++

Import of 3D models of STEP and IDF components

Tracing by groups of signals

T-fan and Fly-By tracing for DDR

Semi-automatic alignment of DDR signal lengths, etc.

Auto-multiplication of trace fragments

Dynamic polygons with auto-update

“Droplets” on sites with DRC provision

Auto-place via arrays

Creation of projects and specifications with “execution options”

Unique features of Cadence Allegro PCB Editor:

Accounting for propagation delay in vias

The editor takes into account the propagation delay along the Z axis in vias, increasing the accuracy of signal propagation delay alignment.

Taking into account different signal delays inside microcircuits

CAD takes into account different signal delays within the chip, increasing the accuracy of length alignment. In-chip delays can be specified in tabular form or imported from a text file.

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Finding cuts in polygons under highways

CAD detects incorrect signal passage over cutouts in the polygon (which may cause signal distortion).

Offset tracing

This is a very relevant function for signals with frequencies above 2 GHz - to solve the problem of path impedance deviation as it passes over fiberglass strands in the dielectric. This allows, by tracing at a non-orthogonal angle, to average the influence of the dielectric structure on the signal quality.

Reverse drilling

CAD supports Back Drilling technology to improve the quality of high-speed signals.

Uniform distribution of traces

Allegro PCB Editor can automatically distribute trace segments evenly to reduce crosstalk from neighbors.

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DRC (Constraint Manager) constraint and rule management system

Setting rules and restrictions using a convenient table

DRC physical limitations (conductors, clearances, restrictions
by length, etc.)

Online DRC checks, rule enforcement

Possibility to highlight DRC violations

Ability to set rules and restrictions in regions

Design for Manufacturing Rules (DFM, DFA)

Checking DRC for the height of components, heatsinks and housing

Possibility to set min. and max. chain length

Limit max. number of circuit vias

Advanced DRC checks such as bare copper etc.

Specctra autorouter

Tracing simultaneously in 6 layers of MPP

Full consideration of specified DRC rules and restrictions

Differences between Allegro and Cadence OrCAD, Altium P-CAD, and other less powerful CAD systems

Component Information System - Unified component database management system

Flow planning application mode - Routing planning using bundles (buses that take into account the number and width of circuits in them)

Dynamic DFA rules based interactive placement - Placement of components using a table of gaps between different ERI housings

Resize/Respace diff pairs - Re-routing of diff pairs with new sizes and gaps is performed automatically throughout the board

Convert corner - conversion of trace corners across the entire board or selected circuits is performed automatically upon your request

Differential pairs dynamic phase control - dynamic phase control on differential pairs is performed automatically

Advanced constraints (formulas, relational) - formulas in constraints, “relative” rules allow you to create sets of rules for the most modern interfaces

Electrical rules (reflection, timing, crosstalk) - control of reflections, timing rules, crosstalk in rules

Package pin delay (for die-2-die delay) rules - taking into account delays inside microcircuit packages

Z-Axis delay feedback - taking into account delays in vias

F2B reuse modules - reuse of "scheme+trace" modules, saving to the library

Contour routing wihile shoving arc routes - routing along a contour, with arcs, automatic routing “along the line”

Removal of unused vias in stack - removing unused vias in the stack

Backdrilling (library or parameter driven) - support for back drilling, either based on a hole library or based on project parameters

Separate backdrilling NC files - separate NC files for back drilling

Speed ​​board routing option

High Speed ​​Option

The Allegro High Speed ​​Option contains all the additional features you need for routing high-speed digital PCBs.

For projects with signal frequencies above 300 MHz (containing PCI Express, DDR2/3/4, GHz Ethernet, GTX, etc. interfaces), it is extremely important to take into account all factors affecting the signal quality on the printed circuit board. The PCB designer needs a tool that not only allows him to effectively align the lengths of signal groups on the board, but also gives him the following capabilities:

Dynamically aligns signal phase throughout the chain to reduce distortion

Semi-automatic alignment of DDR bus lengths

Creating and placing structures from vias,
using them as fanouts

Using via structures on the diff. in pairs
with automatic placement of holes for return flow

Automatic delay equalization

Allegro now performs automatic delay equalization faster and better. This feature is extremely useful because... The number of lines on a printed circuit board that require length alignment is growing and can already range from several tens to several hundred on a typical multilayer board. The editor automatically aligns the length of interactively selected routes in accordance with the specified rules.

Dynamic signal phase control

Allegro allows you to dynamically align the phase of the signal along the entire length of the chain, which is essential for reducing distortion. Moreover, the editor allows you to select exactly that fragment of the trace where the phase mismatch occurred and align the phase locally.

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Teamwork on a project
Symphony Team Design Option

To increase the speed of project completion, you can use the new Symphony Team Design option to organize the joint work of several specialists, this can be done either in the form of breaking the board into parts, which are “sent” to engineers for routing, and then assembled together in one project, or can be organized online work in one project, when everyone sees the actions of other participants through the network.

Dividing the printed circuit board into zones by layers

Dividing the printed circuit board into zones by area

Group PCB tracing

Convenient project control panel

Soft boundaries between zones

Managing Circuit Classes in Zones

View other users' activities

Routing automation

Design Planning

The Design Planning option tools allow you to automate planning and routing, and can be very useful for working with complex projects that have a large number of signal buses and chips with swapping capabilities.

You will be able to lay virtual channels at the placement stage
for conductors to evaluate the feasibility of routing in advance. The width of the channel reflects the actual space required for laying all the conductors in it, taking into account the gaps. With them it is easier to use automatic swap commands, since they will take into account the orientation of the conductors, the side from which they are connected to the microcircuit. After this, the effectiveness of automatic tracing increases noticeably. Conductors are routed in a more orderly manner with fewer vias.

The option includes the following features

Ability to analyze routing feasibility

Drawing a topological routing plan

Auto-generation of conductor topology according to plan

FPGA Pin Optimization Option
FPGA System Planner

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The Allegro FPGA System Planner automates the complex processes of creating FPGA UGOs, determining equivalent pins, swapping pins and blocks, and thereby significantly simplifies and speeds up the development of printed circuit boards.

Designing an FPGA PCB with more than 2000 I/O pins is too complex to do by hand. To complete an FPGA project, constant communication between logic developers and system developers is required
and board developers. Overall, this communication is routine
and even redundant. And it is FPGAs, due to the huge number of multidimensional input-output rules, that make the communication process so complex. These problems can be solved by using an FPGA scheduler that automates all these complex processes.
As a result, the development of printed circuit boards for FPGAs is greatly simplified and accelerated.

The FPGA Scheduler fully automates the processes of associating FPGA pins with other components, generating circuits and routing interconnects, while the following restrictions are observed for all these processes:

Logical restrictions - the pinout must satisfy the protocol requirements of the corresponding interface. For example, for source-synchronous buses, successful data acquisition requires that
both the data and the corresponding clock signals were correctly output to the pins.

Electrical limitations are associated with the FPGA I/O DRC. FPGAs have a complex bank structure and a detailed set of corresponding rules. In order for a bank to be used for an interface, the standard electrical signals of this interface must be specified.

Physical limitations associated with the location of various devices on the board. Pins must be selected to minimize wire crossings and the number of layers required for board routing.

Functionality of the FPGA System Planner option

Accounting for logical, electrical and physical constraints

Auto-selection and optimal exchange of FPGA pins

Auto-generation of UGO symbols for FPGAs

Minimizing signal intersections during routing

A library of accurate and proven FPGA models that contain electrical and pin assignment rules.

Microwave board design option
Analog/RF Option

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The Analog/RF option provides a powerful and flexible set of tools for manual and automatic placement, routing, and editing of microwave layout and analog signals on printed circuit boards, as an add-on built into the standard Allegro PCB Editor.

Because the RF option supports parameterized microwave topology elements, it provides a very simple mechanism for creating, placing, and connecting microwave elements on the board. It allows you to easily trace stripline and microstrip lines with a variety of rotation options, such as "optimally beveled" microwave rotation, rounded or rectangular rotation. It also allows you to directly connect two points with a microwave path or meander with specified properties.

Other functions for routing microwave boards include:

Move, rotate, flip, copy selected microwave components or groups of objects (polygons, lines, topological elements, vias)

Group copying, reflection, rotation of microwave components or sets

Transfer of microwave components or their groups from layer to layer

Changing the microwave parameters of objects and automatically regenerating their shape in accordance with the new parameters

Inserting library microwave components during routing

Electrical calculations and indication of microwave path parameters

Creating your own topological microwave elements

Converting microwave elements to polygons

Converting Allegro editor traces (conductors) to stripline transmission lines

Chamfering corners of microwave routes

Displaying and modifying the values ​​of variables and expressions

Fast multiplication of microwave fragments, including mirroring for symmetrical/balanced circuits

High Density Boards
Miniaturization Option

This option provides additional options when designing boards with micro-vias (blind, blind) and embedded components. Allows you to use cavities inside the board and vertically located components when designing. Adds sets of rules that take into account the nuances of manufacturing the listed elements.

The option includes the following features

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Built-in components in inner layers, easy to add and edit built-in slots

Micro-hole sets - installation on the board with one click, very convenient work with micro-hole sets

HDI Board Rules - a complete set of manufacturing checks for all types of pinholes

Cadence AllegroPCB Design Solution- a scalable, proven PCB development environment designed to solve modern technological and methodological problems, to reduce and increase predictability of development cycles.

Description

Allegro PCB Design Solution comes standard with a variety of options and contains everything you need to create PCB layers in a fully integrated design flow. The Allegro PCBDesigner environment contains everything you need to design simple and complex printed circuit boards

Fig. 1 - The Allegro PCB Designer environment contains everything you need to design simple and complex printed circuit boards

The basic Allegro PCB Designer package includes: a common module, a constraint management environment, a printed circuit board editor, an automatic or interactive router, tools for saving data in industrial formats, and a mechanical design environment for structural components (CAD).

The PCB Editor provides a comprehensive environment from basic planning, placement, and routing to replication and advanced planning with intermediate elements for simple and complex PCB designs (Figure 1).

Advantages

• Is a proven, scalable and cost-effective PCB editing and routing tool, available as standard and with a range of configuration options
• Eliminates unnecessary iterations with constraint-driven design flow
• Supports an extensive set of rules for defining physical sizing, spacing, process, installation and testing (DFx), high-speed interconnect (HDI), and electrical high-speed domains
• Has a general constraint condition management system to create, control and check these conditions from end to end
• Allows interoperability with third-party packages to speed up the design process and leverage the best in integrated development tools

PCB Editor technology

Constraint-Based PCB Editing Environment The main component of Allegro PCB Designer is the PCBEditor layout editor, an intuitive and easy-to-use environment for creating and editing both simple and complex PCB designs that are subject to constraint conditions. DFA (Design For Assembly) placement technology allows components to be placed compactly and accurately

Fig. 2 – Placement technology guided by DFA (Design For Assembly) installation rules allows for compact and error-free placement of components

A wide range of functions meets numerous design and production requirements:

• Powerful set of planning and placement tools, incl. replication to speed up the development process
• Interactive tools for moving, compressing and editing areas create a high-performance real-time interaction environment with display of geometric and temporal boundaries
• Dynamic shapers have functionality for cutting and merging copper polygons during motion and routing iterations
• PCB Editor can also generate a full suite of photomasks, test outputs including Gerber 274x, NC drill and bare-metal PCB inspection tests in a variety of formats.

Managing Constraints

The constraint management system displays real-time geometric dimensions, spacing, high-speed data with compliance status for each development stage. Each worksheet provides an interface for creating, managing, and testing various rules in a hierarchical manner. Using this powerful application, designers can create, edit and view sets of constraint conditions in the form of graphical topologies that act as electronic “light copies” of the ideal implementation strategy. Because constraint conditions are associated with a database, they can guide the placement and routing processes for given signals.

The constraint control system is fully integrated into the PCB Editor and verification can be carried out in real time during the design process. The test results are displayed graphically: areas that successfully passed the test are highlighted in green, and areas that do not meet the limiting conditions are highlighted in red. This allows designers to directly observe the design process and see the effect of any design changes.

Planning and placement

The constraint-driven PCB design methodology includes a flexible and powerful set of automatic and interactive placement tools. An engineer or designer may place components or circuits in special "rooms" during design or planning. Components can be filtered or selected by special designation, chassis or footprint type, network name (title), component number, or table or schematic page number.

This control precision is necessary in modern circuits containing thousands of components. Real-time assembly analysis and feedback helps improve this control, increasing productivity and efficiency by placing components in accordance with corporate rules or recommendations based on electromagnetic simulation results.

Dynamic placement, guided by design-for-assembly rules (DFA), allows each package to be verified during interactive component placement (Figure 2). Feedback generated from a two-dimensional matrix of body classes and prototypes ensures minimum tolerance requirements. Using side-to-side, back-to-back principles, designers can place components to simultaneously achieve optimal routing, manufacturability, and signal properties.

Copying placements

Allegro PCB Designer's superior layout copying technology allows users to quickly place and route similar circuit sections. It allows you to create a circuit and routing template that can be applied to all similar sections of the circuit. The component placement pattern can also be used in other designs with similar circuits. When copying placements, it is possible to rotate or mirror the copied object horizontally or vertically. All elements associated with an object, including hidden blind vias, appear in the correct layers when the object is flipped.

Display and Visualization

All PCB Editor software packages have a built-in 3D visualization tool. The 3D interface supports various filtering options, simulated camera viewing, graphical display options such as solid, transparency and wireframe, and mouse-controlled display panning, zooming and rotating. 3D mode also supports display of complex through-hole structures and isolated sections of the board. Using the contextual control structure, many windows can be opened, and 3D images can be copied and saved in JPEG format (Figure 3).

The ability to flip the board ("flip") allows you to flip the board along the Y axis, accordingly inverting the database at the boundaries. This operation reorganizes the display of the structure so that the top of the structure is at the bottom and the bottom is at the top. It is very important for CAD systems to be able to display bottom views for engineers involved in laboratory debugging of boards or testing during production. The ability to flip the board over isn't just for viewing; it also allows you to make changes to its design. Built-in 3D rendering allows you to view board sections or complex via structures from multiple angles, magnifications, rotations, and rotations to reduce iterations for mechanical designers and PCB manufacturers and prevent the introduction of errors.

Rice. 3 – Built-in 3D rendering allows you to view board sections or complex via structures from multiple angles, magnifications, rotations, and rotations to reduce iterations for mechanical designers and PCB manufacturers and prevent the introduction of errors.

Interactive editing

The PCB Editor Routing Option provides powerful, interactive tools to control the automatic routing process and improve its performance. Working with any shape, angle, or relative movement of components, routing tools allow users to choose different priorities for actions.

During editing, the developer can see in real time how much time remains to complete connections within the specified tight time constraints. The interactive mode also allows for group tracing of many networks and interactive configuration of networks of long length and with restrictions on acceptable delays.

Tire tracing

Bus routing mode (Multi-Line Routing) is designed for routing a large number of lines on a printed circuit board at once. Combined with the “contour capture” option, this utility allows you to trace many lines in a structure containing both flexible and rigid elements in a matter of minutes, while routing individual lines would take hours. The “contour capture” option is responsible for inserting lines into the flexible part of the structure (Fig. 4).

Bus routing with contour capture option speeds up the routing process on flexible areas of PCB designs

Rice. 4 – Bus routing with edge capture option speeds up the routing process on flexible areas of PCB designs

Planning and Routing

Planning and routing high-density PCBs with many constraints and bus connections can take a significant amount of time. Complicating the process is the miniaturization of modern components, new electrical signal levels, and special layout requirements, so it is not surprising that traditional CAD technologies and tools cannot fully realize the designer's intent. Global Route Environment provides the technology to take the designer's intent and stick to it. Thanks to its connection planning architecture and global routing process, for the first time, users can bring their experiences and ideas to life in a tool that understands them naturally.

Users create abstracted link data using a link path planning architecture, quickly convert it into a complete solution, and can validate that solution using a global routing program. The use of connection abstraction makes it possible to reduce the number of elements from tens of thousands to hundreds, which leads to a significant reduction in the amount of direct manual work of the designer.

When using abstract data, the planning and routing process can also be accelerated by applying a spatial visualization of the open area along with the data and the designer's intent. The routing program then works out all the connection details according to that design, without requiring the assistance of the user, who previously had to simultaneously control the routing process and resolve connection problems. The resulting significant simplification of the development process compared to current tools allows users to create effective solutions faster and easier, reducing development cycle times and increasing productivity (Figure 5).

Allegro Interconnect Flow Planner technology allows users to reduce the number of layers and significantly reduce development cycle times

Rice. 5 – Allegro Interconnect Flow Planner allows users to reduce the number of layers and significantly reduce development cycle times

Designing High-Speed ​​Boards

The increasingly widespread use of the latest standard interfaces, such as DDR3, DDR4, PCI Express, USB 3.0, imposes a number of restrictions that must be taken into account when designing a printed circuit board.

Allegro PCB Designer with High-Speed ​​option helps you quickly and easily meet the demands of modern interfaces. This option extends the set of controlled electrical constraints that ensure that the PCB design meets the specifications of modern interfaces.

In addition, High-Speed ​​allows users to enter advanced design rules by using formulas in conjunction with existing rules or resulting data, such as actual wire lengths.

Accelerate time-dependent circuit design

Allegro PCB Editor with High-Speed ​​option significantly speeds up work on high-speed interfaces using the new Auto-interactive Delay Tuning (AiDT) tool. AiDT allows users to quickly adjust the length of a selected set of signals on the board, for example, a byte path or the entire interface. This tool radically reduces development time - from several hours to several minutes (Fig. 6).

Rice. 6 – Automatic adjustment of wire lengths before and after using the new Auto-interactive Delay Tuning tool

Supports reverse drilling technology

Design taking into account production technologies

Allegro PCB Editor supports design-for-test (DfT), design-for-manufacturability (DfF), and design-for-assembly (DfA). All of these critical constraints are checked during the topology design phase, along with electrical constraints. Users can select the number of test points and their pad sizes, define exclusion zones for placing test points, and generate reports to verify the board's readiness for testing. Allegro PCB Editor includes a special function for monitoring DfA rules in real time. With its help, you can monitor and visually track any irregularities on the board related to the gaps between components. When components come close to the maximum distance allowed by DfA rules, the program will automatically issue a warning and “stop” the user before a possible violation of the rules.

Data transfer to production

Allegro PCB Designer can generate a complete set of files for PCB production and testing, including Gerber 274x, NC Drill, NC Route, etc. But most importantly, Cadence supports the industry trend towards "gerberless" manufacturing technology with a new universal IPC-2581 format. The peculiarity of this format is that all data necessary for production, assembly, drilling, milling and testing of the board is stored in one unified file. Users can select data for the IPC-2581 file to protect their intellectual property. Importing IPC-2581 into Allegro PCB Editor allows you to view the file.

Miniaturization

Constraint Driven HDI Design Path

When using BGA packages with pin widths of 1.0-0.8 mm or less, down to 0.5 mm, users must use high-density interconnect (HDI) technology. Although miniaturization is not a primary goal for many market segments, the use of BGAs requires a stacking transition is inevitable when routing complex BGA packages with three or more rows of pins on each side.

Allegro PCB Design, coupled with the Miniaturization Option, provides an end-to-end design path with control of a full set of rules and constraints for a variety of HDI design styles, from hybrid stack/stack to fully process-based stacking, such as ALIVH.

In addition, Allegro PCB Editor includes automatic tools for applying HDI technology to projects to reduce development time and consistently improve designs (iterative design method) (Fig. 7).

Rice. 7 – Dynamic pairing of pads and conductors during interactive routing significantly saves time at the stage of preparing the project for production

Embedded technology support

Reducing the size of the final product can be achieved in various ways. One of them is to place housing elements on the inner layers of the board. Allegro PCB Designer, with the miniaturization option, offers constraint-driven routing technology for embedded components.

It supports both traditional direct and indirect connection technologies, as well as the latest bi-directional connection technologies for a single component, vertical component arrangement, and integrated components for a double-sided board. The miniaturization option allows the user to create and manipulate recesses on layers dedicated to housing embedded components.

Creation of analog RF and microwave boards

Allegro PCB Designer, coupled with Analog/RF Design, provides a mixed-signal design environment from schematic design to historical design to improve RF design productivity by up to 50%. This option allows engineers to create, combine and customize analog RF and microstrip circuits with digital and analog circuits in the Allegro PCB Designer environment. With advanced planning capabilities and powerful interfaces to RF simulation tools, this option allows engineers to begin the RF circuit design process from Allegro Design Authoring, Allegro PCB Designer or Agilent ADS.

Parallel team development

To reduce the duration of the development cycle, geographically dispersed development teams are increasingly being organized. Traditionally used in collaborative development, manual review and refinement procedures are very slow, time-consuming and associated with the risk of introducing errors.

Allegro PCB Design Partitioning technology implements a multi-user parallel design methodology to speed up the process and reduce planning time. With its help, many developers can work simultaneously, having access to a common database regardless of distance. Developers can divide the design process into a number of tasks or areas for which planning and editing will be done, and assign them to several team members. Developments can be divided vertically (sections) with software-defined boundaries or horizontally (layers). As a result, each designer can see all individual sections and see the design process and the results of other designers. The ability to achieve this separation helps to significantly reduce development cycle times and speed up the design process.

Automatic PCB Routing Technology

The Allegro PCB Router's Design For Manufacturing (DFM) tool significantly reduces the number of parts that are subsequently rejected. Its algorithms provide the ability to automatically space conductors using all available free space. Automatic conductor spacing helps improve manufacturability by moving conductors to further increase clearances between conductors and leads, between conductors and SMD pads, and freeing up additional space for conductive pads. Users take advantage of the flexibility to set tolerances either manually or by default.

During routing, free corners and control points can be specified. DFM algorithms automatically make optimal indents, starting with the largest ones and reducing them within accessible limits. The test point creator automatically inserts test vias or pads on the board. Test points in the form of test vias can be located on either the front or back side of the board, allowing the use of single-sided or double-sided testers. Developers have the option of selecting a checkpoint insertion methodology that suits their production requirements. Test points can be fixed to avoid the need to modify the test fixture. Constraints for test points include the surface shape of the test probes, via sizes, grids, and minimum hole center distances.

Automatic constraint-driven routing for high-speed boards

High-speed constraints and routing algorithms use differential pairs, network scheduling, signal timing, crosstalk levels, layer stack routing, and the special geometry requirements of today's high-speed circuits. Automatic routing algorithms accurately route into and around vias and automatically maintain compliance with specified timing or spatial criteria. Automatic network scheduling is used to reduce noise levels in noise-sensitive networks. Separate design rules can be applied to different areas, for example, you can set a rule for maximum density in the area of ​​​​the conductors and less strict rules for the rest of the board.

• added a fully functional ability to load 3D models of components and mechanical parts in STEP format for visual inspection of gaps. A STEP model can be added directly in the symbol editor or topology editor. The special variable steppath specifies the path to the STEP model libraries on the user's local disk or server. The finished topology can now be exported in STEP format to mechanical CAD systems. At the same time, various export options are supported to control the size of the overall STEP board model;

• Added new Auto-Interactive Breakout (AiBT) technology. Its essence lies in the fact that the program, depending on user actions, automatically creates conductors at both ends of the bus or interface. In this case, the circuit lines on the board must be combined into a common bundle. When tracing, a mode is supported where the user can see both ends of the link simultaneously on one screen;

• Added new Auto-Interactive Add Connect (AiCC) tracing tool. This command works in two modes - manual and automatic. Manual mode is no different from the standard Add Connect command. When starting the automatic mode, the user first draws a curved line along the route, and then this curve is converted into a finished route;

• The new Detune command allows you to delete the result of adjusting a single trace or several traces along the length. This function is very convenient if you need to move routes or change delay restrictions.

Overview of printed circuit board design technologies Cadence Allegro PCB Designer

Anatoly Sergeev,
specialist at Orkada for Cadence Design Systems, Inc. products, author of numerous articles. Graduated from Vladimir State University with a degree in “Design and technology of radio-electronic equipment”

The development of electronics is driven by the increasing performance and functionality of semiconductor technologies. New devices are becoming increasingly complex, and component pin configurations, pitch, and packaging density are important design considerations. Also, new devices use modern interfaces: DDR3, DDR4, PCI Express Gen3, USB 3.0 and others, which require new types of implementation on the printed circuit board. All this leads to an ever-increasing demand for new packaging methods that increase the density of interconnects on a printed circuit board. Today, to solve such complex problems, engineers need modern technologies for designing systems at the printed circuit board level that will meet technological and methodological requirements. These include, for example, the Cadence Allegro PCB Designer software package, some of the most important functions of which are described in this publication.

Connection planning and routing

Complex circuit boards with many electrical and process constraints, high component density, and multiple high-speed signal data buses require a new design approach. The use of traditional and outdated CAD systems, such as P-CAD, becomes unacceptable, since they are not able to ensure the readiness of such projects in the shortest possible time. CAD systems are coming to the fore, which are actively developing and meet modern realities in the electronics industry. Cadence Allegro PCB Designer, combined with the Interconnect Flow Planner option, provides a unique feature for creating an interconnect plan and then converting it into a finished routing. This planning and routing mechanism gives the engineer the opportunity to lay large arrays of signals in the form of special objects - signal harnesses, which can significantly simplify the design and radically reduce development time (Fig. 1).

The engineer sees on the screen not hundreds or thousands of intersecting electrical lines, but a plan for laying large arrays of these connections. It is clear that this approach greatly increases the efficiency of work - it is possible to lay signal harnesses between layers, plan the placement of vias, avoid crossing bundles with each other, route signals along the shortest path, etc. For each harness, you can set its own set of properties, ensure its traceability in terms of time s x signal delays in it, copy routing plans between different projects. Allegro PCB Editor at the software level will “tell” the developer the optimal routes for laying the harnesses, and then, using unique algorithms, convert the resulting plan into a finished topology.

Accelerate time-dependent circuit design

The increasingly widespread use of high-speed digital interfaces, such as DDR3, DDR4, PCI Express, USB 3.0, imposes a number of restrictions that must be taken into account when designing a printed circuit board.

Allegro PCB Designer with High-Speed ​​option helps you quickly and efficiently meet the requirements of modern interfaces. This option expands the range of controllable electrical limits that the engineer can use to quickly achieve maximum signal integrity and ensure accurate timing. s e characteristics. Also, along with the High-Speed ​​option in Allegro PCB Designer, powerful tools for managing time-dependent circuits become available, such as Auto-interactive Delay Tuning, Auto-Interactive Phase Tuning, Auto-Interactive Convert Corner, Timing Vision, etc. Let's look at some of them in more detail.

The Auto-interactive Delay Tuning tool, abbreviated as AiDT, gives users the ability to quickly tune the length of a selected set of signals on the board, such as a byte path or an entire interface. This tool radically reduces the timing adjustment time s x delays for a large array of signals - from several hours to several minutes (Fig. 2). The user just needs to draw a selection frame around the desired set of signals, after which the length of the traces will be automatically adjusted in accordance with the parameters specified in the Constraint Manager.

The Auto-Interactive Phase Tuning tool, or AiPT, allows you to achieve optimal dynamic phase for a differential pair in minutes. The dynamic phase means ensuring the equality of the lengths of the conductors, taking into account their bends in different sections of the laying from the source to the signal receiver. Thanks to this tool, the time required to align the lengths of conductors in a differential pair is significantly reduced.

The user must continuously monitor the time-dependent circuits on the board. The specially developed Timing Vision visual inspection environment built into Allegro PCB Editor allows the user to quickly find inappropriate timings. s m trace restrictions on the printed circuit board. This tool includes color indicators, the ability to select a special pattern for routes, and special tooltips. Depending on the specified time s x restrictions in the Constraint Manager, the traces on the board will be highlighted in a different color, which is selected in the settings (Fig. 4).

Rice. 4. Timing Vision tool for visual control of the length of traces, taking into account the time dependence of signals

Design taking into account production technologies

Allegro PCB Editor supports Design for Testability (DFT), Design for Manufacturability (DFF), and Design for Manufacturability (DFA). All of these critical constraints are checked during the topology design phase, along with electrical constraints. Users can select the number of test points and their pad sizes, define exclusion zones for placing test points, and generate reports to verify the board's readiness for testing. Allegro PCB Editor includes a special function for monitoring DFA rules in real time. With its help, you can monitor and visually track any irregularities on the board related to the gaps between components. When components approach the maximum distance allowed by DfA rules, the program will automatically issue a warning and “stop” the user before a possible violation of the rules.

Data transfer to production

Allegro PCB Designer can generate a complete set of files for PCB production and testing, including Gerber 274x, NC Drill, NC Route, etc. But most importantly, Cadence supports the industry's move toward gerberless manufacturing technology with the new universal IPC-2581 format. The peculiarity of this format is that all the data necessary for the production, assembly, drilling, milling and testing of the board is stored in one unified file. Users can select data for the IPC-2581 file to protect their intellectual property. Importing IPC-2581 into Allegro PCB Editor allows you to view the file.

HDI board design route

Miniaturization is the main trend in electronics today. Devices are getting smaller while their performance and functionality are growing. Projects are increasingly using chips in BGA packages with pin pitches of 0.8 mm or less, which requires the use of high-density interconnect (HDI) technology to output signals to internal layers from BGA pads using fanouts. The design of the board in this case requires the use of microvias, placement of software on contact pads, and special manufacturing processes. All this must be taken into account in full by the PCB design system at the design rules control level.

Allegro PCB Designer in combination with the Miniaturization Option allows you to create projects based on HDI technology of any complexity. This includes the following features:

• work with micro holes;
• optimization of mixed vias;
• control of blind and blind holes on the layer;
• control of shelving of transition platforms;
• control of stepwise arrangement of transitions;
• site within a site;
• mass production of transitions;
• control for compliance with manufacturing technology;
• taking into account HDI design rules during automatic routing.

Allegro PCB Designer, combined with the miniaturization option, includes many different interactive routing tools, such as blind and blind hole pushing, dynamic via mating, embedded component support, contour routing for rigid-flex boards, and more (Figure 5).

Embedded technology support

Reducing the size of the final product can be achieved in various ways. One of them is to place housing elements on the inner layers of the board. Allegro PCB Designer, with the miniaturization option, offers constraint-driven routing technology for embedded components. It supports both traditional direct and indirect connection technologies, as well as the latest bi-directional connection technologies for a single component, vertical component arrangement, and integrated components for a double-sided board. The miniaturization option allows the user to create and manipulate recesses on layers dedicated to housing embedded components.

Creation of analog RF and microwave boards

Allegro PCB Designer, coupled with Analog/RF Design, provides a mixed-signal design environment from schematic creation to historical planning to improve RF design productivity by up to 50%. This option allows engineers to create, combine and customize analog RF and microstrip circuits with digital and analog circuits in the Allegro PCB Designer environment. With advanced planning capabilities and powerful interfaces to RF simulation tools, this option gives engineers the ability to start the RF circuit design process from Allegro Design Authoring, Allegro PCB Designer or Agilent ADS.

Parallel team development

To reduce the duration of the development cycle, geographically dispersed development teams are increasingly being organized. Traditionally used in collaborative development, manual review and refinement procedures are very slow, time-consuming and associated with the risk of introducing errors.
Allegro PCB Design Partitioning technology implements a multi-user parallel design methodology to speed up the process and reduce planning time. With its help, many developers can work simultaneously, having access to a common database regardless of distance. Developers can divide the design process into a number of tasks or areas for which planning and editing will be done, and assign them to several team members. Developments can be divided vertically (sections) with software-defined boundaries or horizontally (layers). As a result, each designer can see all individual sections, observe the design process and evaluate the results of other designers. The ability to achieve this separation helps to significantly reduce development cycle times and speed up the design process.

Automatic PCB Routing Technology

PCB routing technologies are closely related to the PCB editor. Through the PCB Router interface, all design information and constraint conditions are automatically received from the PCB editor. At the end of the tracing, all information is automatically transferred back to the PCB editor.

Increased design complexity, density, and additional constraints for high-speed circuits make manual routing difficult and time-consuming. Solving the challenges of tracing complex connections requires powerful, automated technology. The robust and production-proven automatic router features a batch route mode with advanced route strategy control and built-in route strategies.

The Design For Manufacturing (DFM) tool included in the Allegro PCB Router significantly reduces the number of parts that are subsequently rejected. Its algorithms provide the ability to automatically space conductors using all available free space. Automatic conductor spacing helps improve manufacturability by moving conductors to further increase clearances between conductors and leads, between conductors and SMD pads, and freeing up additional space for conductive pads. Users take advantage of the flexibility to set tolerances either manually or by default.

Functions	Allegro PCB Designer
Allegro Design Authoring (Concept HDL) - entering information at the level of diagrams, tables and HDL descriptions
Allegro Design Entry CIS/Capture - schematic capture, centralized component database - CIS, access to the global Internet database of electronic components Active Parts
Constraint-Manager - physical, spatial and single chain rules
Constraint-Manager - changing individual properties of components and DRCs
Constraint-Manager - support for areas with local rules
Layout, placement, template placement Real-time DFA compliance
Supports IDF3.0, DXF in/out formats
New dynamic data exchange format with mechanical CAD systems - IDX (EDMD schema)
3D visualization of a printed circuit board
Hierarchical Interconnect Layout Route
Rules for controlling the length of conductors for high-speed signals
Constraint controlled route for high speed signals depending on wire length
Agreement groups, an individual set of rules for each layer, extended circuits
Rules for T-connections (T-connection at pin)
Automatic meshless tracer (up to six layers)
Automatic routing based on high-speed rules
Automatic routing based on individual rules for each layer
Project planning - spatial planning of the topology based on feasibility and feedback	Design Planning Option
Project Planning - Topology Plan Generation	Design Planning Option
Project Planning - Converting Topology Plan to Alignments (CLINES)	Design Planning Option
Auto-interactive length construction for a selected group of signals	PCB High-Speed ​​Option
Constraint-Manager - electrical rules to account for signal reflection, timing and crosstalk	PCB High-Speed ​​Option
Electrical Rules Controlled Design Route	PCB High-Speed ​​Option
Electrical Rule Sets (ECSets)	PCB High-Speed ​​Option

Functions	Allegro PCB Designer
Mathematical description of design rules	PCB High-Speed ​​Option
Supports reverse drilling technology	PCB High-Speed ​​Option
Dynamic phase control, axis delays Z	PCB High-Speed ​​Option
Return path monitoring to ensure signal integrity	PCB High-Speed ​​Option
Constraint-Manager - a set of rules for HDI projects	Miniaturization Option
Pinholes and associative spatial, batch rules, including via-pad rules	Miniaturization Option
Constraint-driven development path for HDI projects	Miniaturization Option
Support of process rules for the production of boards with embedded components	Miniaturization Option
Support for rules for components embedded on the internal layers of the board	Miniaturization Option
Editing a Pinhole Stack in HDI projects	Miniaturization Option
Dynamic meshless mating, line extension, trace mating	Miniaturization Option
Tracing along a nonlinear contour (for flexible boards)	Miniaturization Option
Support of recesses (voids) on internal layers	Miniaturization Option
Parallel Engineering - Layering	PCB Team Design Option
Parallel engineering - distribution across functional blocks	PCB Team Design Option
Concurrent Engineering - Central status panel to manage the design process	PCB Team Design Option
Parallel Engineering - Chain Distribution	PCB Team Design Option
Editing restrictions between areas	PCB Team Design Option
Managing Net Classes Between Regions	PCB Team Design Option
Editing Parameterized RF Strip Elements	PCB Analog / RF Option
Asymmetrical gaps	PCB Analog / RF Option
Two-way interface with Agilent ADS	PCB Analog / RF Option
Importing Schematics from Agilent ADS into Design Entry Authoring	PCB Analog / RF Option
Design of microwave boards	PCB Analog / RF Option
Built-in polygon editor for microwave topology	PCB Analog / RF Option
Automatic routing up to 256 layers	PCB Routing Option
Automatic routing based on DFM rules	PCB Routing Option
Automatic route distribution	PCB Routing Option
Automatic generation of control points	PCB Routing Option
Tracing based on individual rules for each layer	PCB Routing Option

During routing, free corners and control points can be specified. DFM algorithms automatically make optimal indents, starting with the largest ones and reducing them within accessible limits. The test point creator automatically inserts test vias or pads on the board. Test points in the form of test vias can be located on both the front and back sides of the board, allowing the use of single-sided or double-sided testers. Developers have the option of selecting a checkpoint insertion methodology that suits their production requirements. Test points can be fixed to avoid the need to modify the test fixture. Constraints for test points include the surface shape of the test probes, via sizes, meshes, and minimum hole center distances.

Automatic constraint-driven routing for high-speed boards

High-speed constraint conditions and routing algorithms apply differential pairs, network planning, timing s e signal parameters, crosstalk levels, layer stack routing, and special geometry requirements for today's high-speed circuits. Automatic routing algorithms accurately route into and around vias and automatically maintain compliance with specified timings. s m or spatial criteria. Automatic network scheduling is used to reduce noise levels in noise-sensitive circuits. You can apply different design rules to different areas of the board, for example, you can set a rule for maximum density in the area of ​​\u200b\u200bthe conductors and less strict rules for the rest of the board.

The development of high-speed electronics must be supported by adequate software and hardware design tools. Allegro PCB Designer is a powerful tool in the hands of a professional designing modern, high-speed electronics. The latest update, Update Release No. 2, released in March of this year, includes a large number of new work tools, which were partially described in this article.

microcontroller and various additional devices: permanent and random access memory, keyboard, as well as graphic and alphanumeric liquid crystal displays.

As of December 2014, the current version of MultiSim 13.X is current.

Rice. 11. Results of the Ultiboard program

Rice. 12. Working window of the MultiSim 20 program

Micro-CAP (Spectrum Software). Micro-Cap (Microcomputer Circuit Analysis Program) – professional

A program for analog, digital and mixed modeling and analysis of circuits of electronic devices of medium complexity.

The program was written in 1982 by Spectrum Software, and since then it has been constantly expanded and improved. The company, in turn, was founded by Andy Thompson in February 1980, initially positioning itself on writing programs for Apple. It is located in one of the cities of Silicon Valley - Sunnyvale (California, USA).

An intuitive interface, low demands on PC computing resources and a wide range of capabilities have made Micro-Cap popular among professionals and students. The operating algorithm includes creating an electrical circuit in a graphical editor (Fig. 13), setting analysis parameters and analyzing the obtained data. The program independently compiles the circuit equations and performs instant calculations. Any change in the schema or element parameters results in automatic updating of the results.

Rice. 13. Working window of the Micro-Cap program

The graphic editor relies on libraries of electronic components, which can be expanded based on experimental or reference data using the built-in Shape Editor module. All ratings and parameters of the elements can be either constant or dependent on temperature, time, frequency, state of the circuit, and parameters of other components.

Animated parts (LEDs, relays, seven-segment indicators and some other elements) change state in accordance with the signals received by them. The simulation includes a variety of analyzes (Figure 14): transients, DC transfer characteristics, small-signal frequency responses, DC sensitivities, harmonic distortions, Monte Carlo and many others. Experienced users can create their own macromodels that facilitate simulation without loss of information. It is possible to simultaneously use different standards for circuit elements. Full support for Spice models allows you to use projects from other programs (DesignLab, OrCAD, P-CAD). The only disadvantage we can note is the need to install additional elements, since the volume of Micro-Cap libraries (even in the full version) is clearly insufficient.

The Micro-Cap Active Filter Designer program (Fig. 15) offers the ability to automatically calculate active and passive Butterworth, Chebyshev, Bessel, elliptical filters: low frequencies, high frequencies, bandpass, notch. The created filter can be inserted into the project. Designer also offers the user a choice of op amps to use in active filters. It can create filters for either exact value or standard impedance values.

Rice. 14. Working window of the results of the Micro-Cap program

Rice. 15. Working window of the Micro-Cap Active filter designer program

The cost of Micro-Cap is several thousand dollars, but on the developer's website you can download the freely distributed Evaluation Version, which has many of the features of the full-featured version. The main differences are no more than 50 elements in the circuit, a reduced library of components, restrictions on the construction of a number of graphs, and slow speed.

The latest version as of December 2014 is Micro-Cap 11 (2013).

4. SYSTEMS FOR "END-TO-END" DESIGN OF ELECTRONIC DEVICES

4.1. Cadence Products

The technologies of one of the leading companies - developers of "electronic" CAD systems from Cadence Design Systems - cover almost all stages of the design of complex electronic devices and systems - from the system level, characteristic of developers of final equipment, to the levels of logical, circuit and topological design of very large-scale integrated circuits (VLSI) , their packaging, as well as the development of printed circuit boards on which these VLSIs will be mounted.

Cadence Design Systems currently has a group of programs united on the Cadence SPB (Silicon – Package – PCB) platform, formerly PCB Design Studio. Some of them are Cadence’s own development (Allegro, Specctra), some were acquired through a merger with OrCAD Systems (OrCAD Capture, PSpice).

The platform concept is aimed at the ultimate goal - the creation of an “electronic” product and includes both the development of VLSI (chips) and their cases, as well as printed circuit boards (Fig. 16). The modern approach involves the use of a single information space at all these and subsequent stages of the life cycle of the designed product.

Rice. 16. Concept of the Cadence SPB platform

Trying to take the best from each part, Cadence increases the degree of integration of its programs with each version, often using the term OrCAD/Allegro. At the same time, there is a division between these products: OrCAD can be positioned as a design system for “simple” projects, Allegro – for more complex ones. Accordingly, their functionality, requirements and costs differ.

Cadence SPB (PCB Design Studio) currently includes:

Orcad Capture CIS – circuit editor with integrated management tools and Internet access to a database of standard components;

Rice. 17. Scalability of Cadence OrCAD/Allegro

Concept HDL is an alternative circuit editor. Typically used for reuse of designs and collaboration between engineers. Each of the two editors has their own approaches and strengths. Orcad Capture CIS is used to work on a simple project. Concept HDL is suitable for teams developing more complex projects. In this case, all work can be divided into single-task modules and distributed among designers;

PSpice/AMS Simulator – program for modeling analog and mixed devices;

PE Librarian – a program designed for creating component libraries and managing these libraries;

OrCAD/Allegro PCB Editor is a topological editor of printed circuit boards, used for placing and editing designs of electronic components and conductors, as well as for preparing devices for production;

SPECCTRA – contains the Placement Editor component placement editor and the Route Editor semi-automatic meshless conductor routing editor;

SPECCTRA Autorouter – automatic wire router (also meshless); OrCAD/Allegro PCB Signal Integrity is a signal integrity analysis program.

Orcad Capture. The Cadence OrCAD Capture program (since DOS versions) has become the de facto standard in its field thanks to its convenient, intuitive interface and the presence of diverse functions for quickly performing the necessary actions. To speed up the design process, a CIS (Component Interchange System) “add-on” is used, which provides access to reference information from manufacturers of electronic components both via the Internet and through a central database.

Search tools allow you to find the components you need using various parameters as search criteria. Once a component has been found, CIS rewrites all its data: logical, physical, manufacturer data, ordering information, etc. and supports access to them from OrCAD Capture. If components, database or schema are modified, the update occurs with the click of a button. Bi-directional integration with PCB editor ensures schematic compliance

And topology in case of rearrangement of individual elements, pins or changes in parameters and names of components.

Main features of OrCAD Capture:

1. Circuit editor is built on the traditional OrCAD Capture interface (Fig. 18), which combines intuitiveness with the tools and functionality necessary to solve circuit design problems. For more complex diagrams, a multi-page

And hierarchical mode of operation. The system ensures neat connections between all parts of the circuit.

2. Central information system ensures synchronization of external data with information within the project. Using the Microsoft ODBC standard, the system can be integrated with any of the well-known databases, from Excel or Access to MRP, ERP or PLM systems. The flexibility of the system allows several users to simultaneously access information without interference.

Rice. 18. OrCAD Capture window

3. Component Selection. Thanks to quick access, a convenient search system and the ability to add components to a project directly from an external database, CIS significantly reduces PCB development time. Adding components directly from the central database (Figure 19) reduces the likelihood of errors in listing items and allows you to control the use of components that meet different standards.

4. Finding components online. One of the features in CIS is the ability to search for items over the Internet using the Internet Component Assistant (ICA). As with the internal database, any electrical or commercial component properties can be searched. The free database, called Cadence ActiveParts, contains more than two million components that can be searched by criteria and previewed before adding to the schema.

Rice. 19. Structure of working with the central database using the example of a component library

5. Integration with other OrCAD products. Two-way integration with OrCAD/Allegro PCB Editor

ensures error-free transfer of data from the circuit to the printed circuit board and vice versa. Synchronization of the circuit is automated after the permitted replacement of conductors on the board. Ensures end-to-end identification of conductors and components. OrCAD Capture has the ability to create a netlist for other CAD systems.

6. Possibility of creating diagrams and lists of elements according to GOST.

As of December 2014, the latest version is Cadence OrCAD Capture 16.6 (2014).

OrCAD/Allegro PCB Editor. The OrCAD/Allegro PCB Editor is considered one of the best in the world in its class. It is an interactive shell for creating and editing complex multilayer printed circuit boards. Its extensive capabilities meet the most modern requirements. In it, Cadence first used the concept of “rules-driven” design: restrictions on the placement of components, combining them into groups, setting the width of conductors for critical circuits, etc. (Fig. 20).

Rice. 20. Rules (right) for technological placement of components on a printed circuit board (left)

Modern PCB manufacturing requires highly sophisticated and powerful metallization layer design tools. It is necessary to reduce the number of these layers to a minimum to reduce the final cost of the product. This problem is solved by the Allegro PCB system, which contains highly efficient tools for planning and editing layers of printed circuit boards to create uniform power dissipation on it. The system includes tools for selecting and dividing the PCB layout into layers, negative or positive representation of internal metallization layers, as well as various options that allow the user to define fragments of power layers. The user is provided with a complete set of tools for making photomasks and printed circuit boards, as well as testing them (including a table of Gerber 274x apertures; an NCDrill table containing information about the total number, coordinates and sizes of holes, as well as various drawings of printed circuit boards). Full integration of the package with internal or specific external systems used in a particular production is possible (Fig. 21).

The range of functions allows you to solve many design and production problems. The powerful system for planning and placing components and their groups includes the ability to copy topology fragments as template modules to radically reduce the placement phase.

Creating and editing topology on printed circuit boards is based on technologies for pushing and bending various objects - conductors, vias - in real time, which provides visual control over the established rules of lengths and delays. Rupture and restoration in dynamic polygons while placing components and laying routes occurs in real time.

With PCB Editor you can also produce a complete set of files for photo plotter, PCB part processing and testing files (Gerber 274x, NC drill, etc.).

Rice. 21. OrCAD/Allegro PCB Editor window

The following options can be connected to OrCAD/Allegro PCB Editor.

RF option. Development of high-frequency (HF) and microwave board topologies. Many modern digital printed circuit boards contain circuits that operate in the radio frequency range. These circuits have specific requirements and are typically designed and simulated in the Agilent ADS design environment (formerly Agilent EEsof). However, these circuits must be on the same circuit board with other digital and analog circuits. To do this, in the OrCAD/Allegro PCB Editor, during the PCB design process, there is the ability to import RF blocks designed in Agilent ADS, and in addition, a number of possibilities for working with such components:

creation of new RF components;

settings RF components;

use of RF elements when tracing;

transfer of RF elements or groups from layer to layer;

calculation of electrical parameters of strip lines;

converting RF components into polygons;

converting traces into strip lines and parameterizing “strips”. Miniaturization option. Microminiaturization:

pinhole and spatial, batch rules, including rules like “via in pad”;

support for rules for boards with built-in components;

support for rules for components built into the internal layers of the board;

tracing along a nonlinear contour (for flexible boards);

dynamic reinforcement of conductors at the boundary of the flexible and rigid parts;

control of multi-tiered microtransitions.

The PCB Team Design option allows multiple engineers to collaborate asynchronously in a hierarchical product development process. The project can be divided into predefined hierarchical levels and distributed among team members, giving each engineer an isolated space to develop and verify their part of the project.

FPGA System Planner Option. Optimization of FPGAs for printed circuit boards.

Option for 3D visualization of the printed circuit board. An example of using this option is shown in Fig. 22.

Rice. 22. 3D visualization of a printed circuit board

PSpice/AMS Simulator. The PSpice/Allegro AMS Smulator program is used to perform analog numerical simulations. The user can configure the symbols on the diagram in such a way as to match them with the Spice model and carry out numerical simulations. You can also easily match electrical circuit diagram components, their location on the circuit board, and simulation results to quickly determine various characteristics (Figure 23).

Rice. 23. Correspondence between the components of the electrical circuit diagram,

their location on the printed circuit board and simulation results in PSpice/Allegro AMS Simulator

OrCAD/Allegro is compatible with Microsoft products and provides the ability to configure the command bar. Using a specialized language, you can customize the environment to suit your requirements and desires.

The new Cadence strategy does not involve the constant release of new versions, but their updates (according to statements once a quarter). Distribution of the program is paid, but there is a trial version of the latest one

December 2014 program version – OrCAD/Allegro SPB 16.6.

SPECCTRA. SPECCTRA is an automatic PCB routing program from Cadence Design Systems. Sometimes it is called Allegro PCB Router. As of December 2014, the latest version is 16.5.

The SPECCTRA program successfully traces highly complex boards thanks to the use of a new principle for presenting graphic data, the so-called ShapeBased technology. Unlike previously known packages, in which graphic objects are presented as a set of coordinates of points, this program uses more compact methods for their mathematical description. Due to this, the efficiency of routing printed circuit boards with a high density of components increases, automatic routing of the same circuit with traces of different widths is ensured, etc.

The SPECCTRA autorouter uses adaptive algorithms that are implemented over several tracing passes. On the first pass, absolutely all conductors are connected without paying attention to possible conflicts consisting in the intersection of conductors on the same layer and violation of the gaps. On each subsequent pass, the autorouter tries to reduce the number of conflicts by breaking and re-laiding connections (rip-up-and-retry method) and pushing conductors, pushing apart neighboring ones (push-and-shove method). Information about conflicts on the current trace pass is used for “training” - changing the weighting coefficients (penalties) so that by changing the strategy, reduce the number of conflicts on the next pass.

Conductor routing is carried out in three stages: preliminary routing, auto-routing, and additional processing of auto-routing results.

All tracing phases are performed interactively or automatically using a set of special commands (Fig. 24).

Rice. 24. Screen of the SPECCTRA program in the interactive component placement mode